Method for measuring number of yield loss chips and number of poor chips by type due to defect of semiconductor chips

ABSTRACT

A method for measuring the number of yield loss chips and the number of poor chips by type due to defects of semiconductor chips by which it is possible to remarkably improve the yield of semiconductor chips by measuring the number of yield loss chips due to defects of the chips, the maximum number of yield loss chips, and the number of the specific type of poor chips in an arbitrary process, an arbitrary equipment, and an arbitrary process section among semiconductor fabrication processes, thus managing the defects of the chips, is provided. 
     The method for measuring the number of yield loss chips and the number of poor chips by type due to defects of semiconductor chips includes the steps of checking defective chips among effective chips on a wafer which underwent a predetermined process using a defect examination equipment and plotting the checked defective chips on a first wafer map, forming disparity chips by pairing defective chips and non-defective chips adjacent to the defective chips on the first wafer map and determining a maximum reliability region formed of regions in which the disparity chips are located, plotting good chips and poor chips by type on a second wafer map using a yield measuring apparatus after completing the process, and classifying the number of good chips and poor chips by type on the second wafer map corresponding to the defective chips and the non-defective chips in the maximum reliability region on the first wafer map.

TECHNICAL FIELD

The present invention relates to a method for measuring an accuratevalue of yield loss due to chip defect caused by the inflow of dust orforeign material or due to poor shapes of chips during semiconductormanufacturing processes.

BACKGROUND ART

Defects of wafer chips caused by dust, foreign material, and poor shapesof the chips during semiconductor manufacturing processes criticallyaffect the yield and characteristics of chips. Such a defect isgenerated in all handling processes including environment as well as allequipments and all semiconductor manufacturing processes. Thus, thismakes the range of management of defects required by field managers verybroad. Accordingly, production and quality management of chips isdifficult.

Defects of chips critically affect the yield loss and characteristics ofthe chips. The yield loss is generally 1 through 30% of defective chips.Namely, the degree of yield loss varies according to processes withrespect to the same numbers of defective chips. The degree of the yieldloss varies according to products. The degree of the yield loss variesaccording to the degree and type of defects.

For example, in the case of a dynamic random access memory (DRAM), apoor chip is obtained when a defect exists outside a memory cell region.However, when a defect exists inside the memory cell region, a good chipcan be obtained by performing a laser repair using a redundancy cell.Namely, the degree of yield loss varies in the same chip according tothe positions of the defect.

Since the causes of yield loss during the fabrication of thesemiconductor chips are derived from all processes such as aphotolithography process, an etching process, a diffusion process, anion implantation process, and a thin film deposition process as well asthe above defects, it is difficult to determine how much effect defectshave on yield loss.

It is difficult to manage yield by managing defects since the degree ofyield loss varies according to products when defects are generated, thedegree of the yield loss varies according to processes with respect tothe same product, and defects are generated in all processes,equipments, circumstances, and handling processes of a semiconductorfabrication field.

It is possible to measure the total number of defects generated on awafer, the total number of defective chips by the degree and type ofdefects with current technology of measuring yield loss andcharacteristics of the chip according to the defects. It is possible toanalyze and measure the amount of yield loss to the total number ofdefects, the number of specific poor chips to the total number ofdefects, the yield loss amount to the total number of defective chips,and the number of specific poor chips to the total number of defectivechips by matching the measurement result to the yield measurement resultand statistically processing the result.

Accordingly, when the total number of defects or the total number ofdefective chips increases, the yield loss amount and specific defectratio also increase. Namely, it is possible to relatively measure theamount of yield loss to the total number of defects, the number ofspecific poor chips to the total number of defects, the yield lossamount to the total number of defective chips, and the number ofspecific poor chips to the total number of defective chips.

As mentioned above, since the causes of yield loss exist in allprocesses, it is not possible to measure the absolute value of the yieldloss by which it is possible to determine how much the chips in whichthe yield loss occurs are affected by the defect.

DISCLOSURE OF THE INVENTION

It is a first object of the present invention to provide a method formeasuring the number of yield loss chips and the number of poor chips bytype due to the defects of semiconductor chips by which it is possibleto remarkably improve the yield of semiconductor chips by accuratelyobtaining the number of the yield loss chips due to defects of thechips, the maximum number of yield loss chips, and the number ofspecific types of poor chips in an arbitrary process, an arbitraryequipment, and an arbitrary process section among semiconductorfabrication processes, thus managing the defects of the chips.

It is a second object of the present invention to provide a computerreadable medium on which the above method realized as a program isrecorded.

Accordingly, to achieve the first object, there is provided a method formeasuring the number of yield loss chips and the number of poor chips bytype due to defects of semiconductor chips, comprising the steps ofchecking defective chips among effective chips on a wafer whichunderwent a predetermined process using a defect examination equipmentand plotting the checked defective chips on a first wafer map, formingdisparity chips by pairing defective chips and non-defective chipsadjacent to the defective chips on the first wafer map and determining amaximum reliability region formed of regions in which the disparitychips are located, plotting good chips and poor chips by type on asecond wafer map using a yield measuring apparatus after completing theprocess, and classifying the number of good chips and poor chips by typeon the second wafer map corresponding to the defective chips and thenon-defective chips in the maximum reliability region on the first wafermap.

Accordingly, to achieve the second object, there is provided a computerreadable medium including program commands for measuring the number ofthe yield loss chips and the number of poor chips by type due to thedefect of semiconductor chips, the computer readable medium comprising acomputer readable code for inputting data on defective chips andnon-defective chips among effective chips on a wafer which underwent apredetermined process from a defect examination equipment and plottingthe input data on the defective chips and the non-defective chips on afirst wafer map, a computer readable code for forming disparity chips bypairing the defective chips and the non-defective chips adjacent to thedefective chips on the first wafer map and determining the maximumreliability region comprised of regions in which the disparity chips arelocated, a computer readable code for inputting data on good chips andpoor chips by type from a yield measuring apparatus and plotting theinput data on the good chips and the poor chips on a second wafer map,and a computer readable code for classifying the number of the goodchips and the poor chips by type on the second wafer map correspondingto the defective chips and the non-defective chips in the maximumreliability region on the first wafer map and mapping out the statisticswith respect to the yield loss and the number of the poor chips by type.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will becomemore apparent by describing in detail a preferred embodiment thereofwith reference to the attached drawings in which:

FIG. 1 shows a wafer map on which defective chips among effective chipsare plotted on a wafer using a defect examination equipment according tothe present invention;

FIG. 2 shows a wafer map on which disparity chips are formed based on adefective chip pattern according to the present invention;

FIG. 3 explains a method of constituting the disparity chips accordingto the present invention;

FIG. 4 shows a wafer map on which a maximum reliability region fixed bythe combination of disparity chips according to the present invention isdisplayed;

FIG. 5 shows a wafer map on which effective chips on a wafer areclassified into good chips and poor chips using a yield measuringapparatus according to the present invention; and

FIG. 6 shows a wafer map on which good chips and poor chips by type inthe maximum reliability region according to the present invention areextracted.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described indetail with reference to the attached drawings.

In an embodiment of the present invention, in the first step, defectivechips among effective chips on a wafer are plotted on a first wafer mapusing a defect examination equipment as shown in FIG. 1. FIG. 1 shows afirst wafer map on which an effective chip region 11 comprised of 77chips is constituted of twenty-two (22) defective chips 12 havingdefects 14 and fifty-five (55) non-defective chips 13 on a wafer 10.

In the second step referred to by FIG. 2, a disparity chip 15 is formedon the first wafer map by pairing each defective chip 12 confirmed inthe first step and each non-defective chip 13 adjacent thereto.

In FIG. 3, a disparity chip is formed by sequentially searching fordefective chips on the wafer map and combining the defective chips withnon-defective chips directly above, below, to the left and right amongthe non-defective chips which did not form the disparity chip 15. Sincethe defective chips are collectively generated, the defective chipswhich do not form the disparity chip 15, that is, a non-disparity chip16 can deteriorate reliability. Therefore, the non-disparity chip 16 isexcluded from data which form the reliability region for generatingstatistics according to the present invention.

In the third step, referring to FIG. 4, a maximum reliability region 17formed by combining the disparity chips formed in the second step isfixed on the first wafer map.

In the fourth step, referring to FIG. 5, good chips A and poor chips B,C, D, E, and F are plotted on the second wafer map using the yieldmeasuring apparatus. FIG. 5 shows the second wafer map on which goodchips and poor chips are plotted.

In the fifth step, referring to FIG. 6, good chips A and poor chips B,C, D, E, and F on the second wafer map, resulting from the measurementof the yield in the fourth step are extracted from the maximumreliability region on the first wafer map.

In the sixth step, as shown in Table 1, all the disparity chips in themaximum reliability region are classified into defective chips andnon-defective chips. The classified defective chips and non-defectivechips are respectively classified into good chips, poor chips, andinferiority types.

TABLE 1 Number Number of good of poor Inferiority types chips chipsTotal B C D E F Defective chips 12 10 22 4 3 1 1 1 Non-defective chips15  7 22 2 2 1 1 1

In the seventh step, the generation ratios of the good chips and thepoor chips to the defective chips and the generation ratios according toinferiority types and generation ratio of good chips and poor chips tonon-defective chips and the generation ratios according to inferioritytypes are calculated as follows.

Defective chips:

The generation ratio of good chips: 12/22=0.545 (a)

The generation ratio of poor chips: 10/22=0.455 (b)

The generation ratio of B type inferiority: 4/22=0.182 (c)

The generation ratio of C type inferiority: 3/22=0.136 (d)

The generation ratio of D type inferiority: 1/22=0.045 (e)

The generation ratio of E type inferiority: 1/22=0.045 (f)

The generation ratio of F type inferiority: 1/22=0.045 (g)

Non-defective chips:

The generation ratio of good chips: 15/22=0.682 (h)

The generation ratio of poor chips: 7/22=0.318 (i)

The generation ratio of B type inferiority: 2/22=0.091 (j)

The generation ratio of C type inferiority: 2/22=0.091 (k)

The generation ratio of D type inferiority: 1/22=0.045 (l)

The generation ratio of E type inferiority: 1/22=0.045 (m)

The generation ratio of F type inferiority: 1/22=0.045 (n).

In step 8, the sum of yield losses according to the current level, theoptimal level, and the worst level is calculated by the process providedin Table 2 using the various generation ratios calculated in the step 7.

TABLE 2 Number of Yield loss of non- non- defective defective chipschips Total Number of Yield loss of number of defective defective Sum ofchips chips chips yield losses Current 77 55 17.49  27.5 (o) level (55 ×0.318) 22 10.01 (22 × 0.455) Optimal 77 77 24.49 24.49 (p) level (77 ×0.318)  0 0 (0 × 0.455) Worst 77  0 0 (0 × 0.318) 35.04 (q) level 7735.04 (77 × 0.455)

Current level refers to a state in which there are fifty-five (55)non-defective chips and twenty-two (22) defective chips. Optimal levelrefers to a state in which all chips are non-defective chips. Worstlevel refers to a state in which all chips are defective chips.

In the ninth step, the number of yield loss chips according to defectsand the maximum number of yield loss chips are calculated as followsbased on the sum of yield losses obtained in step 8.

The number of yield loss chips due to defects=the current level value(o)−the optimal level value (p)=27.5−24.49=3.01 chips.

The maximum number of yield loss chips=the worst level value (q)−theoptimal level value (p)=35.04−24.49=10.55 chips.

Here, in the current level (the total number of chips: 77 and the numberof the defective chips : 22), the yield loss (3.01/77=3.91%) of the 3.01chips is generated due to the defects. A maximum yield loss(10.55/77=13.7%) of 10.55 chips may be generated by the defects.

It is possible to produce processes of inferiority generation of thecurrent level, the optimal level, and the worst level according to theinferiority type from the various generation ratios calculated in theseventh step. The total number of B-type poor chips according to thecurrent level, the optimal level, and the worst level in the inferioritytype B are calculated by the processes provided in Table 3.

TABLE 3 Number of B type poor chips of non- Number of defective non-chips defective Number of B chips type poor Total Total Number of chipsof number of B number of defective defective type poor chips chips chipschips Current 77 55 5.01  9.01 (o) level (55 × 0.091) 22 4.00 (22 ×0.182) Optimal 77 77 7.01  7.01 (p) level (77 × 0.091)  0 0 (0 × 0.182)Worst 77  0 0 (0 × 0.091) 14.01 (q) level 77 14.01 (77 × 0.182)

It is possible to obtain the generation ratio of B-type inferiority andthe maximum generation ratio of B-type inferiority.

The number of chips in which B-type specific inferiority is generateddue to defects=the current level value (r)—the optimal level value(s)=9.01−7.01=2 chips.

The maximum number of chips in which the B type specific inferiority maybe generated=the worst level value (t)—the optimal level value(s)=14.01−7.01=7 chips.

It is noted from the above that the B-type of inferiority (2/77=2.60%)is generated in two chips due to the defects in the current level (thetotal number of chips: 77 and the number of the defective chips: 22) andthat the B-type of inferiority (7177=9.09%) may be generated in amaximum of 7 chips due to the defects.

Also, the total number of C-type poor chips according to the currentlevel, the optimal level, and the worst level in the C type inferioritytype can be calculated by the processes provided in Table 4.

TABLE 4 Number of C type poor chips of non- Number of defective non-chips defective Number of C chips type poor Total Total Number of chipsof number of C number of defective defective type poor chips chips chipschips Current 77 55 5.01  8.00 (u) level (55 × 0.091) 22 2.99 (22 ×0.136) Optimal 77 77 7.01  7.01 (v) level (77 × 0.091)  0 0 (0 × 0.136)Worst 77  0 0 (0 × 0.091) 10.47 (w) level 77 10.47 (77 × 0.136)

It is possible to obtain the generation ratio of C-type inferiority andthe maximum generation ratio of C-type inferiority.

The number of chips in which C-type inferiority is generated due todefects=the current level value (u)—the optimal level value(v)=8.00−7.01=0.99 chips.

The maximum number of chips in which C-type inferiority may begenerated=the worst level value (w)—the optimal level value(v)=10.47−7.01=3.46 chips.

It is noted from the above that the C-type of inferiority(0.99/77=1.29%) is generated in 0.99 chips due to the defects in thecurrent level (the total number of chips: 77 and the number of thedefective chips: 22) and that the C-type of inferiority (3.46/77=4.49%)may be generated in a maximum of 3.46 chips due to the defects.

Also, it is possible to obtain the inferiority generation ratio and themaximum inferiority generation ratio by the same method as used in theB-type and C-type of inferiority.

The above-mentioned embodiment can be made out as a program which can beexecuted by computers. The embodiment can be realized by general purposedigital computers which operate program from a computer readable medium.The computer readable medium may include a magnetic storing medium suchas a ROM, a floppy disk, and a hard disk, an optical reading medium suchas a CD-ROM and a DVD, and carrier waves, for example, transmissionthrough the Internet.

Functional programs, codes, and code segments for realizing the presentinvention can be easily referred to by programmers in the art.

Industrial Applicability

As mentioned above, according to the present invention, it is possibleto accurately measure the absolute values of the yield loss and thespecific inferiority types due to the defects by clarifying the yieldloss process after completely removing the influences of other processelements than the defects through a maximum reliability region designmethod constituted of only the disparity chip. Therefore, it is possibleto accurately check the yield loss due to defects with respect to a unitprocess, a unit equipment, and a unit process section on the basis ofthe absolute values. Accordingly, it is possible to set the managementorder of priority and the management level with respect to criticalprocesses, critical equipment, and critical process sections by correctnumbers, to thus reasonably manage defects. Accordingly, it is possibleto improve yield.

What is claimed is:
 1. A method for measuring the number of yield losschips and the number of poor chips by type due to defects ofsemiconductor chips, comprising the steps of: (a) checking defectivechips among effective chips on a wafer which underwent a predeterminedprocess using a defect examination equipment and plotting the checkeddefective chips on a first wafer map; (b) forming disparity chips bypairing defective chips and non-defective chips adjacent to thedefective chips on the first wafer map and determining a maximumreliability region formed of regions in which the disparity chips arelocated; (c) plotting good chips and poor chips by type on a secondwafer map using a yield measuring apparatus after completing theprocess; and (d) classifying the number of good chips and poor chips bytype on the second wafer map corresponding to the defective chips andthe non-defective chips in the maximum reliability region on the firstwafer map, wherein, in the step (b), disparity chips are formed bysequentially searching defective chips on a wafer map and by combiningthe defective chip searched among non-defective chips which did not forma disparity chip with non-defective chips directly above, below, to theleft and right and the defective chips which are not combined with theadjacent non-defective chips among the searched defective chips areexcluded from the maximum reliability region.
 2. A method for measuringthe number of yield loss chips and the number of poor chips by type dueto defects of semiconductor chips, comprising the steps of: (a) checkingdefective chips among effective chips on a wafer which underwent apredetermined process using a defect examination equipment and plottingthe checked defective chips on a first wafer map; (b) forming disparitychips by pairing defective chips and non-defective chips adjacent to thedefective chips on the first wafer map and determining a maximumreliability region formed of regions in which the disparity chips arelocated; (c) plotting good chips and poor chips by type on a secondwafer map using a yield measuring apparatus after completing theprocess; and (d) classifying the number of good chips and poor chips bytype on the second wafer map corresponding to the defective chips andthe non-defective chips in the maximum reliability region on the firstwafer map, wherein the step (d) comprises the steps of: (d1) classifyingthe number of good chips and poor chips on a second wafer map,corresponding to defective chips and non-defective chips in the maximumreliability region on a first wafer map; and (d2) obtaining thegeneration ratio of poor chips and inferiority generation ratio by typeto the defective chips and the generation ratio of the poor chips andthe inferiority generation ratio by type to the non-defective chipsbased on the number of good chips and poor chips by type classified inthe step (d1).
 3. The method of claim 2, wherein the step (d) furthercomprises the step of (d3) obtaining the sum of the yield loss accordingto a current level, an optimal level, and a worst level and the totalnumber of poor chips by type, based on the generation ratio of poorchips and inferiority generation ratio by type to the defective chipsand the generation ratio of the poor chips and the inferioritygeneration ratio by type to the non-defective chips.
 4. The method ofclaim 3, wherein the step (d) further comprises the step of (d4)obtaining the number of yield loss chips, the maximum number of yieldloss chips, and the ratio of the maximum number of yield loss chips tothe number of yield loss chips and the number of chips in whichinferiority is generated by type, the maximum number of chips in whichinferiority may be generated, and the ratio of the maximum number ofchips in which inferiority may be generated to the number of chips inwhich inferiority is generated by type.
 5. A method for measuring thenumber of yield loss chips and the number of poor chips by type due todefects of semiconductor chips, comprising the steps of: (a) checkingdefective chips among effective chips on a wafer which underwent apredetermined process using a defect examination equipment and plottingthe checked defective chips on a first wafer map; (b) forming disparitychips by pairing defective chips and non-defective chips adjacent to thedefective chips on the first wafer map and determining a maximumreliability region formed of regions in which the disparity chips arelocated; (c) plotting good chips and poor chips by type on a secondwafer map using a yield measuring apparatus after completing theprocess; (d) classifying the number of good chips and poor chips by typeon the second wafer map corresponding to the defective chips and thenon-defective chips in the maximum reliability region on the first wafermap; and (e) obtaining the generation ratio of poor chips andinferiority generation ratio by type to the defective chips and thegeneration ratio of the poor chips and the inferiority generation ratioby type to the non-defective chips based on the number of good chips andpoor chips by type classified in the step (d).
 6. The method of claim 5wherein, in the step (b), disparity chips are formed by sequentiallysearching defective chips on a wafer map and by combining the defectivechip searched among non-defective chips which did not form a disparitychip with non-defective chips directly above, below, to the left andright and the defective chips which are not combined with the adjacentnon-defective chips among the searched defective chips are excluded fromthe maximum reliability region.
 7. The method of claim 5 furthercomprising the step of: (f) obtaining the sum of the yield lossaccording to a current level, an optimal level, and a worst level andthe total number of poor chips by type, based on the generation ratio ofpoor chips and inferiority generation ratio by type to the defectivechips and the generation ratio of the poor chips and the inferioritygeneration ratio by type to the non-defective chips.
 8. The method ofclaim 7 further comprising the step of: (g) obtaining the number ofyield loss chips, the maximum number of yield loss chips, and the ratioof the maximum number of yield loss chips to the number of yield losschips and the number of chips in which inferiority is generated by type,the maximum number of chips in which inferiority may be generated, andthe ratio of the maximum number of chips in which inferiority may begenerated to the number of chips in which inferiority is generated bytype.